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Developer’s Manual March, 2003 2-11
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Programming Model
2.3.3 Additions to CP15 Functionality
To accommodate the functionality in the Intel
®
80200 processor, registers in CP15 and CP14 have
been added or augmented. See Chapter 7, “Configuration” for details.
At times it is necessary to be able to guarantee exactly when a CP15 update takes effect. For
example, when enabling memory address translation (turning on the MMU), it is vital to know
when the MMU is actually guaranteed to be in operation. To address this need, a processor-specific
code sequence is defined for each Intel
®
StrongARM* processor. For the Intel
®
80200 processor,
the sequence -- called CPWAIT -- is shown in Example 2-1 on page 2-11.
Example 2-1. CPWAIT: Canonical method to wait for CP15 update
When setting multiple CP15 registers, system software may opt to delay the assurance of their
update. This is accomplished by emitting CPWAIT only after the sequence of MCR instructions.
The CPWAIT sequence guarantees that CP15 side-effects are complete by the time the CPWAIT is
complete. It is possible, however, that the CP15 side-effect takes place before CPWAIT completes
or is issued. Programmers should take care that this does not affect the correctness of their code.
;; The following macro should be used when software needs to be
;; assured that a CP15 update has taken effect.
;; It may only be used while in a privileged mode, because it
;; accesses CP15.
MACRO CPWAIT
MRC P15, 0, R0, C2, C0, 0 ; arbitrary read of CP15
MOV R0, R0 ; wait for it
SUB PC, PC, #4 ; branch to next instruction
; At this point, any previous CP15 writes are
; guaranteed to have taken effect.
ENDM