B-4 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Optimization Guide
B.2.1.3. Out Of Order Completion
Sequential consistency of instruction execution relates to two aspects: first, to the order in which
the instructions are completed; and second, to the order in which memory is accessed due to load
and store instructions. The Intel
®
80200 processor preserves a weak processor consistency because
instructions may complete out of order, provided that no data dependencies exist.
While instructions are issued in-order, the main execution pipeline, memory, and MAC pipelines
are not lock-stepped, and, therefore, have different execution times. This means that instructions
may finish out of program order. Short ‘younger’ instructions may be finished earlier than long
‘older’ ones. (The term ‘to finish’ is used here to indicate that the operation has been completed
and the result has been written back to the register file.)
B.2.1.4. Register Scoreboarding
In certain situations, the pipeline may need to be stalled because of register dependencies between
instructions. A register dependency occurs when a previous MAC or load instruction is about to
modify a register value that has not been returned to the register file and the current instruction
needs access to the same register. Only the destination of MAC operations and memory loads are
scoreboarded. The destinations of ALU instructions are not scoreboarded.
If no register dependencies exist, the pipeline is not stalled. For example, if a load operation has
missed the data cache, subsequent instructions that do not depend on the load may complete
independently.
B.2.1.5. Use of Bypassing
The Intel
®
80200 processor pipeline makes extensive use of bypassing to minimize data hazards.
Bypassing allows results forwarding from multiple sources, eliminating the need to stall the
pipeline.