Filter
Top Products
13-52 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Software Debug
13.15.2.4 High-Speed Download
Special debug hardware has been added to support a high-speed download mode to increase the
performance of downloads to system memory (vs. writing a block of memory using the standard
handshaking).
The basic assumption is that the debug handler can read any data sent by the debugger and write it
to memory, before the debugger can send the next data. Thus, in the time it takes for the debugger
to scan in the next data word and do an Update_DR, the handler is already in its polling loop,
waiting for it. Using this assumption, the debugger does not have to poll RR to see whether the
handler has read the previous data - it assumes the previous data has been consumed and
immediately starts scanning in the next data word.
The pitfall is when the write to memory stalls long enough that the assumption fails. In this case the
download with normal handshaking can be used (or high-speed download can still be used, but a
few extra TCKs in the Pause_DR state may be necessary to allow a little more time for the store to
complete).
The hardware support for high-speed download includes the Download bit (DCSR[29]) and the
Overflow Flag (DCSR[30]).
The download bit acts as a branch flag, signalling to the handler to continue with the download.
This removes the need for a counter in the debug handler.
The overflow flag indicates that the debugger attempted to download the next word before the
debugger read the previous word.
More details on the Download bit, Overflow flag and high-speed download, in general, can be
found in Section 13.8, Transmit/Receive Control Register (TXRXCTRL).
Following is example code showing how the Download bit and Overflow flag are used in the
debug handler:
hs_write_word_loop:
hs_write_overflow:
bl read_RX @ read data word from host
@@ read TXRXCTRL into the CCs
mrc p14, 0, r15, c14, c0, 0
bcc hs_write_done @ if D bit clear, download complete, exit loop.
beq hs_write_overflow @ if overflow detected, loop until host clears D bit
str r0, [r6], #4 @ store only if there is no overflow.
b hs_write_word_loop @ get next data word
hs_write_done:
@@ after the loop, if the overflow flag was set, return error message to host
moveq r0, #OVERFLOW_RESPONSE
beq send_response
b write_common_exit