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Developer’s Manual March, 2003 4-1
Instruction Cache
4
The Intel
®
80200 processor based on Intel
®
XScale
™
microarchitecture (compliant with the
ARM* Architecture V5TE) instruction cache enhances performance by reducing the number of
instruction fetches from external memory. The cache provides fast execution of cached code. Code
can also be locked down when guaranteed or fast access time is required.
4.1 Overview
Figure 4-1 shows the cache organization and how the instruction address is used to access the
cache.
The instruction cache is a 32-Kbyte, 32-way set associative cache; this means there are 32 sets with
each set containing 32 ways. Each way of a set contains eight 32-bit words and one valid bit, which
is referred to as a line. The replacement policy is a round-robin algorithm and the cache also
supports the ability to lock code in at a line granularity.
The instruction cache is virtually addressed and virtually tagged.
Note: The virtual address presented to the instruction cache may be remapped by the PID register. See
Section 7.2.13, “Register 13: Process ID” on page 7-16 for a description of the PID register.
Figure 4-1. Instruction Cache Organization
way 0
way 1
way 31
8 Words (cache line)
Set 31
CAM
DATA
way 0
way 1
way 31
8 Words (cache line)
Set 1
CAM
DATA
way 0
way 1
way 31
8 Words (cache line)
Set Index
Set 0
Tag
Instruction Word
(4 bytes)
Instruction Address (Virtual)
31 109 54 210
Tag Set Index Word
Word Select
CAM
DATA
This example
shows Set 0 being
selected by the
set index.
CAM: Content
Addressable Memory