Filter
Top Products
1-4 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Introduction
1.1.2.6 Power Management
The Intel
®
80200 processor supports two low power modes: idle and sleep. These modes are
discussed in Section 8.3, “Power Management” on page 8-5.
1.1.2.7 Interrupt Controller
An interrupt controller is implemented on the Intel
®
80200 processor that provides masking of
interrupts and the ability to steer interrupts to FIQ or IRQ. It is accessed through Coprocessor 13
registers. See Chapter 9, “Interrupts”for more detail.
1.1.2.8 Bus Controller
The Intel
®
80200 processor supports a pipelined external bus that runs at 100 MHz. The data bus is
32/64 bits with ECC protection. The bus controller can be configured to provide critical word first
on load operations, enhancing overall system performance. The bus controller has four request
queues, where all four requests can be active on the pipelined external bus.
Chapter 10, “External Bus” describes the external bus protocol and Chapter 11, “Bus Controller”
covers the aspects of ECC protection. The bus controller registers are accessed via coprocessor 13.
1.1.2.9 Performance Monitoring
Two performance monitoring counters have been added to the Intel
®
80200 processor that can be
configured to monitor various events in the Intel
®
80200 processor. These events allow a software
developer to measure cache efficiency, detect system bottlenecks and reduce the overall latency of
programs.
Chapter 12, “Performance Monitoring”discusses this in more detail.
1.1.2.10 Debug
The Intel
®
80200 processor supports software debugging through two instruction address
breakpoint registers, one data-address breakpoint register, one data-address/mask breakpoint
register, and a trace buffer.
Chapter 13, “Software Debug”discusses this in more detail.
1.1.2.11 JTAG
Testability is supported on the Intel
®
80200 processor through the Test Access Port (TAP)
Controller implementation, which is based on IEEE 1149.1 (JTAG) Standard Test Access Port and
Boundary-Scan Architecture. The purpose of the TAP controller is to support test logic internal and
external to the Intel
®
80200 processor such as built-in self-test, boundary-scan, and scan.
Appendix C.2 discusses this in more detail.