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Developer’s Manual March, 2003 13-7
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Software Debug
During Halt mode, software running on the Intel
®
80200 processor cannot access DCSR, or any of
hardware breakpoint registers, unless the processor is in Special Debug State (SDS), described
below.
When a debug exception occurs during Halt mode, the processor takes the following actions:
• disables the trace buffer
• sets DCSR.moe encoding
• processor enters a Special Debug State (SDS)
• for data breakpoints, trace buffer full break, and external debug break:
R14_dbg = PC of the next instruction to execute + 4
for instruction breakpoints and software breakpoints and vector traps:
R14_dbg = PC of the aborted instruction + 4
• SPSR_dbg = CPSR
• CPSR[4:0] = 0b10101 (DEBUG mode)
• CPSR[5] = 0
• CPSR[6] = 1
• CPSR[7] = 1
• PC = 0x0
1
Following a debug exception, the processor switches to debug mode and enters SDS, which allows
the following special functionality:
• All events are disabled. SWI or undefined instructions have unpredictable results. The
processor ignores pre-fetch aborts, FIQ and IRQ (SDS disables FIQ and IRQ regardless of the
enable values in the CPSR). The processor reports data aborts detected during SDS by setting
the Sticky Abort bit in the DCSR, but does not generate an exception (processor also sets up
FSR and FAR as it normally would for a data abort).
• Normally, during halt mode, software cannot write the hardware breakpoint registers or the
DCSR. However, during the SDS, software has write access to the breakpoint registers (see
Section 13.6, HW Breakpoint Resources) and the DCSR (see Table 13-1, “Debug Control and
Status Register (DCSR)” on page 13-3).
• The IMMU is disabled. In halt mode, since the debug handler would typically be downloaded
directly into the IC, it would not be appropriate to do TLB accesses or translation walks, since
there may not be any external memory or if there is, the translation table or TLB may not
contain a valid mapping for the debug handler code. To avoid these problems, the processor
internally disables the IMMU during SDS.
• The PID is disabled for instruction fetches. This prevents fetches of the debug handler code
from being remapped to a different address than where the code was downloaded.
The SDS remains in effect regardless of the processor mode. This allows the debug handler to
switch to other modes, maintaining SDS functionality. Entering user mode may cause
unpredictable behavior. The processor exits SDS following a CPSR restore operation.
When exiting, the debug handler should use:
subs pc, lr, #4
This restores CPSR, turns off all of SDS functionality, and branches to the target instruction.
1. When the vector table is relocated (CP15 Control Register[13] = 1), the debug vector is relocated to 0xffff0000