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7-20 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Configuration
7.3 CP14 Registers
Table 7-21 lists the CP14 registers implemented in the Intel
®
80200 processor.
7.3.1 Registers 0-3: Performance Monitoring
The performance monitoring unit contains a control register (PMNC), a clock counter (CCNT),
and two event counters (PMN0 and PMN1). The format of these registers can be found in
Chapter 12, “Performance Monitoring”, along with a description on how to use the performance
monitoring facility.
Opcode_2 and CRm should be zero.
7.3.2 Register 4-5: Reserved
These registers are reserved. Reading and writing them yields unpredictable results.
Table 7-21. CP14 Registers
Register (CRn) Access Description
0-3 Read / Write Performance Monitoring Registers
4-5 Unpredictable Reserved
6-7 Read / Write Clock and Power Management
8-15 Read / Write Software Debug
Table 7-22. Accessing the Performance Monitoring Registers
Function CRn (Register #) Instruction
Read PMNC 0b0000 MRC p14, 0, Rd, c0, c0, 0
Write PMNC 0b0000 MCR p14, 0, Rd, c0, c0, 0
Read CCNT 0b0001 MRC p14, 0, Rd, c1, c0, 0
Write CCNT 0b0001 MCR p14, 0, Rd, c1, c0, 0
Read PMN0 0b0010 MRC p14, 0, Rd, c2, c0, 0
Write PMN0 0b0010 MCR p14, 0, Rd, c2, c0, 0
Read PMN1 0b0011 MRC p14, 0, Rd, c3, c0, 0
Write PMN1 0b0011 MCR p14, 0, Rd, c3, c0, 0