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Developer’s Manual March, 2003 2-3
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Programming Model
2.3 Extensions to ARM* Architecture
The Intel
®
80200 processor made a few extensions to the ARM Version 5 architecture to meet the
needs of various markets and design requirements. The following is a list of the extensions which
are discussed in the next sections.
• A DSP coprocessor (CP0) has been added that contains a 40-bit accumulator and new
instructions.
• New page attributes were added to the page table descriptors. The C and B page attribute
encoding was extended by one more bit to allow for more encodings: write allocate and
mini-data cache. An attribute specifying ECC for 1Meg regions was also added.
• Additional functionality has been added to coprocessor 15. Coprocessor 14 was also created.
• Enhancements were made to the Event Architecture, instruction cache and data cache parity
error exceptions, breakpoint events, and imprecise external data aborts.
2.3.1 DSP Coprocessor 0 (CP0)
The Intel
®
80200 processor adds a DSP coprocessor to the architecture for the purpose of
increasing the performance and the precision of audio processing algorithms. This coprocessor
contains a 40-bit accumulator and new instructions.
The 40-bit accumulator is referenced by several new instructions that were added to the
architecture; MIA, MIAPH and MIAxy are multiply/accumulate instructions that reference the
40-bit accumulator instead of a register specified accumulator. MAR and MRA provide the ability
to read and write the 40-bit accumulator.
Access to CP0 is always allowed in all processor modes when bit 0 of the Coprocessor Access
Register is set. Any access to CP0 when this bit is clear causes an undefined exception. (See
Section 7.2.15, “Register 15: Coprocessor Access Register” on page 7-18 for more details). Note
that only privileged software can set this bit in the Coprocessor Access Register.
The 40-bit accumulator needs to be saved on a context switch if multiple processes are using it.
Two new instruction formats were added for coprocessor 0: Multiply with Internal Accumulate
Format and Internal Accumulate Access Format. The formats and instructions are described next.