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Developer’s Manual March, 2003 13-49
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Software Debug
13.15.2 Implementing a Debug Handler
The debugger uses the debug handler to examine or modify processor state by sending commands
and reading data through JTAG. The API between the debugger and debug handler is specific to a
debugger implementation. Intel provides a standard debug handler and API which can be used by
third-party vendors. Issues and details for writing a debug handler are discussed in this section and
in the Intel Debug Handler.
13.15.2.1 Debug Handler Entry
When the debugger requests an external debug break or is waiting for an internal break, it should
poll the TR bit through JTAG to determine when the processor has entered Debug Mode. The
debug handler entry code must do a write to TX to signal the debugger that the processor has
entered Debug Mode. The write to TX sets the TR bit, signalling the host that a debug exception
has occurred and the processor has entered Debug Mode. The value of the data written to TX is
implementation defined (debug break message, contents of register to save on host, etc.).
13.15.2.2 Debug Handler Restrictions
The Debug Handler executes in Debug Mode which is similar to other privileged processor modes,
however, there are some differences. Following are restrictions on Debug Handler code and
differences between Debug Mode and other privileged modes.
• The processor is in Special Debug State following a debug exception, and thus has special
functionality as described in Section 13.5.1, Halt Mode.
• Although address translation and PID remapping are disabled for instruction accesses (as
defined in Special Debug State), data accesses use the normal address translation and PID
remapping mechanisms.
• Debug Mode does not have a dedicated stack pointer, DBG_r13. Although DBG_r13 exists, it
is not a general purpose register. Its contents are unpredictable and should not be relied upon
across any instructions or exceptions. However, DBG_r13 can be used, by data processing
(non RRX) and MCR/MRC instructions, as a temporary scratch register.
• The following instructions should not be executed in Debug Mode, they may result in
unpredictable behavior:
LDM
LDR w/ Rd=PC
LDR w/ RRX addressing mode
SWP
LDC
STC
• The handler executes in Debug Mode and can be switched to other modes to access banked
registers. The handler must not enter User Mode; any User Mode registers that need to be
accessed can be accessed in System Mode. Entering User Mode may cause unpredictable
behavior.