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Developer’s Manual March, 2003 14-1
Performance Considerations
14
This chapter describes relevant performance considerations that compiler writers, application
programmers and system designers need to be aware of to efficiently use Intel
®
80200 processor
based on Intel
®
XScale
™
microarchitecture (compliant with the ARM* Architecture V5TE).
Performance numbers discussed here include interrupt latency, branch prediction, and instruction
latencies.
14.1 Interrupt Latency
Table 14-1 shows the Minimum Interrupt Latency for the Intel
®
80200 processor, which is the
minimum number of cycles from the assertion of any interrupt signal (IRQ or FIQ) to the execution
of the instruction at the vector for that interrupt.
Note: This number assumes that the interrupt vector is resident in the instruction cache. The Intel
®
80200
processor does provide the capability to lock the vector and the interrupt service routine into the
instruction cache.
Many parameters can affect this best-case performance:
• instruction currently executing: could be as bad as a 16-register LDM
• fault status: processor could fault just when the interrupt arrives
• stalls: processor could be waiting for data from a load, doing a page table walk, etc.
• bus ratio: the best case assumes a 3:1 core:bus ratio. Higher ratios would slightly improve
performance
Table 14-1. Minimum Interrupt Latency
# MCLK Clock Cycles Description
3
Minimum Interrupt Latency
. This is measured from the assertion of IRQ or FIQ
interrupt pin to the execution of the first instruction of the interrupt event handler.