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Developer’s Manual March, 2003 2-1
Programming Model
2
This chapter describes the programming model of the Intel
®
80200 processor based on Intel
®
XScale
™
microarchitecture, namely the implementation options and extensions to the ARM*
Version 5 architecture.
The ARM* Architecture Version 5TE Specification (ARM DDI 0100E) describes Version 5TE of
the ARM Architecture, including the Thumb* ISA and ARM DSP-Enhanced ISA.
2.1 ARM* Architecture Compliance
The Intel
®
80200 processor implements the integer instruction set architecture specified in ARM*
Version 5TE. T refers to the Thumb instruction set and E refers to the DSP-Enhanced instruction
set.
ARM* Version 5 introduces a few more architecture features over Version 4, specifically the
addition of tiny pages (1 Kbyte), a new instruction (CLZ) that counts the leading zeroes in a data
value, enhanced ARM-Thumb transfer instructions and a modification of the system control
coprocessor, CP15.
2.2 ARM* Architecture Implementation Options
2.2.1 Big Endian versus Little Endian
The Intel
®
80200 processor supports both big and little endian data representation. The B-bit of the
Control Register (Coprocessor 15, register 1, bit 7) selects big and little endian mode. To run in big
endian mode, the B bit must be set before attempting any sub-word accesses to memory, or
undefined results occur. Note that this bit takes effect even if the MMU is disabled.
2.2.2 26-Bit Code
The Intel
®
80200 processor does not support 26-bit code.
2.2.3 Thumb*
The Intel
®
80200 processor supports the Thumb instruction set.