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Developer’s Manual March, 2003 6-5
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Data Cache
6.2 Data Cache and Mini-Data Cache Operation
The following discussions refer to the data cache and mini-data cache as one cache
(data/mini-data) since their behavior is the same when accessed.
6.2.1 Operation When Caching is Enabled
When the data/mini-data cache is enabled for an access, the data/mini-data cache compares the
address of the request against the addresses of data that it is currently holding. If the line containing
the address of the request is resident in the cache, the access “hits’ the cache. For a load operation
the cache returns the requested data to the destination register and for a store operation the data is
stored into the cache. The data associated with the store may also be written to external memory if
write-through caching is specified for that area of memory. If the cache does not contain the
requested data, the access ‘misses’ the cache, and the sequence of events that follows depends on
the configuration of the cache, the configuration of the MMU and the page attributes, which are
described in Section 6.2.3.2, “Read Miss Policy” on page 6-6 and Section 6.2.3.3, “Write Miss
Policy” on page 6-7 for a load “miss” and store “miss” respectively.
6.2.2 Operation When Data Caching is Disabled
The data/mini-data cache is still accessed even though it is disabled. If a load hits the cache it
returns the requested data to the destination register. If a store hits the cache, the data is written into
the cache. Any access that misses the cache does not allocate a line in the cache when it’s disabled,
even if the MMU is enabled and the memory region’s cacheability attribute is set.
6.2.3 Cache Policies
6.2.3.1 Cacheability
Data at a specified address is cacheable given the following:
• the MMU is enabled
• the cacheable attribute is set in the descriptor for the accessed address
• and the data/mini-data cache is enabled