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7-18 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Configuration
7.2.15 Register 15: Coprocessor Access Register
This register is selected when opcode_2 = 0 and CRm = 1.
This register controls access rights to all the coprocessors in the system except for CP15 and CP14.
Both CP15 and CP14 can only be accessed in privilege mode. This register is accessed with an
MCR or MRC with the CRm field set to 1.
This register controls access to CP0 and CP13 for the Intel
®
80200 processor. A typical use for this
register is for an operating system to control resource sharing among applications. Initially, all
applications are denied access to shared resources by clearing the appropriate coprocessor bit in the
Coprocessor Access Register. An application may request the use of a shared resource (e.g., the
accumulator in CP0) by issuing an access to the resource, which results in an undefined exception.
The operating system may grant access to this coprocessor by setting the appropriate bit in the
Coprocessor Access Register and return to the application where the access is retried.
Sharing resources among different applications requires a state saving mechanism. Two possibilities
are:
• The operating system, during a context switch, could save the state of the coprocessor if the
last executing process had access rights to the coprocessor.
• The operating system, during a request for access, saves off the old coprocessor state and saves
it with last process to have access to it.
Under both scenarios, the OS needs to restore state when a request for access is made. This means
the OS has to maintain a list of what processes are modifying CP0 and their associated state.
Example 7-1. Disallowing access to CP0
;; The following code clears bit 0 of the CPAR.
;; This will cause the processor to fault if software
;; attempts to access CP0.
LDR R0, =0x0000 ; bit 0 is clear
MCR P15, 0, R0, C15, C1, 0 ; move to CPAR
CPWAIT ; wait for effect