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Developer’s Manual March, 2003 6-7
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Data Cache
6.2.3.3 Write Miss Policy
A write operation that misses the cache requests a 32-byte cache line from external memory if the
access is cacheable and write allocation is specified in the page. In this case the following sequence
of events occur:
1. The fill buffer is checked to see if an outstanding fill request already exists for that line.
If so, the current request is placed in the pending buffer and waits until the previously
requested fill completes, after which it writes its data into the recently allocated cache line.
If there is no outstanding fill request for that line, the current store request is placed in the fill
buffer and a 32-byte external memory read request is made. If the pending buffer or fill buffer
is full, the Intel
®
80200 processor stalls until an entry is available.
2. The 32-bytes of data can be returned back to the Intel
®
80200 processor in any word order, i.e,
the eight words in the line can be returned in any order. Note that it does not matter, for
performance reasons, which order the data is returned to the Intel
®
80200 processor since the
store operation has to wait until the entire line is written into the cache before it can complete.
3. When the entire 32-byte line has returned from external memory, a line is allocated in the
cache, selected by the round-robin pointer (see Section 6.2.4, “Round-Robin Replacement
Algorithm” on page 6-8). The line to be written into the cache may replace a valid line
previously allocated in the cache. In this case both dirty bits are examined and if any are set,
the four words associated with a dirty bit that’s asserted are written back to external memory as
a 4 word burst operation. This write operation is placed in the write buffer.
4. The line is written into the cache along with the data associated with the store operation.
If the above condition for requesting a 32-byte cache line is not met, a write miss causes a write
request to external memory for the exact data size specified by the store operation, assuming the
write request doesn’t coalesce with another write operation in the write buffer.
6.2.3.4 Write-Back Versus Write-Through
The Intel
®
80200 processor supports write-back caching or write-through caching, controlled
through the MMU page attributes. When write-through caching is specified, all store operations are
written to external memory even if the access hits the cache. This feature keeps the external
memory coherent with the cache, i.e., no dirty bits are set for this region of memory in the
data/mini-data cache. This however does not guarantee that the data/mini-data cache is coherent
with external memory, which is dependent on the system level configuration, specifically if the
external memory is shared by another master.
When write-back caching is specified, a store operation that hits the cache does not generate a write
to external memory, thus reducing external memory traffic.