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13-38 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Software Debug
13.14.4 Loading IC During Reset
Code can be downloaded into the instruction cache through JTAG during a processor reset. This
feature is used during software debug to download the debug handler prior to starting an
application program. The downloaded handler can then intercept the reset vector and do any
necessary setup before the application code executes
In general, any code downloaded into the instruction cache through JTAG, must be downloaded to
addresses that are not already valid in the instruction cache. Failure to meet this requirement results
in unpredictable behavior by the processor. During a processor reset, the instruction cache is
typically invalidated, with the exception of the following modes:
• LDIC mode: active when LDIC JTAG instruction is loaded in the JTAG IR; prevents the mini
instruction cache and the main instruction cache from being invalidated during reset.
• HALT mode: active when the Halt Mode bit is set in the DCSR; prevents only the mini
instruction cache from being invalidated; main instruction cache is invalidated by reset.
During a cold reset (in which both a processor reset and a JTAG reset occurs) it can be guaranteed
that the instruction cache is invalidated since the JTAG reset takes the processor out of any of the
modes listed above.
During a warm reset, if a JTAG reset does not occur, the instruction cache is not invalidated by
reset when any of the above modes are active. This situation requires special attention if code needs
be downloaded during the warm reset.
Note that while Halt Mode is active, reset can invalidate the main instruction cache. Thus debug
handler code downloaded during reset can only be loaded into the mini instruction cache. However,
code can be dynamically downloaded into the main instruction cache. (refer to Section 13.14.5,
Dynamically Loading IC After Reset).
The following sections describe the steps necessary to ensure code is correctly downloaded into the
instruction cache.