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13-20 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Software Debug
13.11.2.2 DBG.BRK
DBG.BRK allows the debugger to generate an external debug break and asynchronously re-direct
execution to a debug handling routine.
A debugger sets an external debug break by scanning data into the DBG_SR with DBG_SR[2] set
and the desired value to set the DCSR JTAG writable bits in DBG_SR[34:3].
Once an external debug break is set, it remains set internally until a debug exception occurs. In
Monitor mode, external debug breaks detected during abort mode are pended until the processor
exits abort mode. In Halt mode, breaks detected during SDS are pended until the processor exits
SDS. When an external debug break is detected outside of these two cases, the processor ceases
executing instructions as quickly as possible. This minimizes breakpoint skid, by reducing the
number of instructions that can execute after the external debug break is requested. However, the
processor continues to process any instructions which may have already begun execution. Debug
mode is not entered until all processor activity has ceased in an orderly fashion.
13.11.2.3 DBG.DCSR
The DCSR is updated with the value loaded into DBG.DCSR following an Update_DR. Only bits
specified as writable by JTAG in Table 13-1 are updated.
13.11.3 DBGTX JTAG Command
The ‘DBGTX’ JTAG instruction selects the DBGTX JTAG data register. The JTAG opcode for this
instruction is ‘0b10000’. Once the DBGTX data register is selected, the debugger can receive data
from the debug handler.