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Developer’s Manual March, 2003 10-21
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
External Bus
10.3.7 Pipelined Accesses
The example in Figure 10-11 demonstrates the four deep pipelined nature of this bus. In this
example, the Intel
®
80200 processor is bus limited and is issuing requests as quickly as it can.
Before time 0ns, there are no outstanding transactions. Two reads (A and B) followed by a write
(C) and another read (D) are all requested before 85 ns in this timing diagram.
Because the Intel
®
80200 processor may have up to four outstanding transactions, and in this
example only three are outstanding at time 85 ns, it can send another request (for E) at time 90 ns.
If none of the transactions had completed, the E transaction would have been delayed.
Figure 10-11. Pipeline Example
Rd A Rd B Wr C Rd D Rd E
0x581 0x35C. 0x0 0x970. 0x100.
Rd A Rd B3. R B0 Rd B1.Rd B2. Wr C Rd
0xF0
0
0
0
0x0
1
1
0
0x0
0
1
0
0x240
0
1
0
0x0
0
1
0
0x55
0ns 25ns 50ns 75ns 100ns 125ns
MCLK
nADS/LEN[2]
Lock/LEN[1]
WnR/LEN[0]
A
DValid
CWF
D
nBE
DCB
Abort