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C-14 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Test Features
Figure C-4. Timing Diagram Illustrating the Loading of Instruction Register
TCK
TMS
Controller State
TDI
Data input to IR
IR shift-register
Parallel output of IR
Data input to TDR
TDR shift-register
Parallel output of TDR
Register selected
TDO enable
TDO
Test-Logic-Reset
Exit1 - IR
Shift - IR
Capture - IR
Select - IR - Scan
Select - DR - Scan
Run - Test / Idle
Pause - IR
Exit2 - IR
Shift - IR
Exit1 - IR
Update - IR
Run - Rest / Idle
INACTIVEACTIVEINACTIVEINACTIVE
ACT
OLD DATA
= Don't care or undefined
NEW INSTRUCTION
idcode
INSTRUCTION REGISTER