Filter
Top Products
14-8 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Performance Considerations
14.4.5 Saturated Arithmetic Instructions
h
14.4.6 Status Register Access Instructions
14.4.7 Load/Store Instructions
Table 14-10. Saturated Data Processing Instruction Timings
Mnemonic Minimum Issue Latency Minimum Result Latency
QADD 1 2
QSUB 1 2
QDADD 1 2
QDSUB 1 2
Table 14-11. Status Register Access Instruction Timings
Mnemonic Minimum Issue Latency Minimum Result Latency
MRS 1 2
MSR 2 (6 if updating mode bits) 1
Table 14-12. Load and Store Instruction Timings
Mnemonic Minimum Issue Latency Minimum Result Latency
LDR 1 3 for load data; 1 for writeback of base
LDRB 1 3 for load data; 1 for writeback of base
LDRBT 1 3 for load data; 1 for writeback of base
LDRD 1 (+1 if Rd is R12) 3 for Rd; 4 for Rd+1; 2 for writeback of base
LDRH 1 3 for load data; 1 for writeback of base
LDRSB 1 3 for load data; 1 for writeback of base
LDRSH 1 3 for load data; 1 for writeback of base
LDRT 1 3 for load data; 1 for writeback of base
PLD 1 N/A
STR 1 1 for writeback of base
STRB 1 1 for writeback of base
STRBT 1 1 for writeback of base
STRD 2 1 for writeback of base
STRH 1 1 for writeback of base
STRT 1 1 for writeback of base
Table 14-13. Load and Store Multiple Instruction Timings
Mnemonic Minimum Issue Latency
1
1. LDM issue latency is 7 + N if R15 is in the register list and 2 + N if it is not. STM issue latency is calculated as 2 + N. N is
the number of registers to load or store.
Minimum Result Latency
LDM 3 - 23 1-3 for load data; 1 for writeback of base
STM 3 - 18 1 for writeback of base