Filter
Top Products
13-2 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Software Debug
13.3 Introduction
The Intel
®
80200 processor debug unit, when used with a debugger application, allows software
running on a the Intel
®
80200 processor target to be debugged. The debug unit allows the debugger
to stop program execution and re-direct execution to a debug handling routine. Once program
execution has stopped, the debugger can examine or modify processor state, co-processor state, or
memory. The debugger can then restart execution of the application.
On the Intel
®
80200 processor, one of two debug modes can be entered:
• Halt mode
• Monitor mode
13.3.1 Halt Mode
When the debug unit is configured for halt mode, the reset vector is overloaded to serve as the
debug vector. A new processor mode, DEBUG mode (CPSR[4:0] = 0x15), is added to allow debug
exceptions to be handled similarly to other types of ARM* exceptions.
When a debug exception occurs, the processor switches to debug mode and redirects execution to a
debug handler, via the reset vector. After the debug handler begins execution, the debugger can
communicate with the debug handler to examine or alter processor state or memory through the
JTAG interface.
The debug handler can be downloaded and locked directly into the instruction cache through JTAG
so external memory is not required to contain debug handler code.
13.3.2 Monitor Mode
In monitor mode, debug exceptions are handled like ARM prefetch aborts or ARM data aborts,
depending on the cause of the exception.
When a debug exception occurs, the processor switches to abort mode and branches to a debug
handler using the pre-fetch abort vector or data abort vector. The debugger then communicates with
the debug handler to access processor state or memory contents.