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Developer’s Manual March, 2003 v
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
6.2.3.3 Write Miss Policy ......................................................................................7
6.2.3.4 Write-Back Versus Write-Through ............................................................7
6.2.4 Round-Robin Replacement Algorithm .........................................................................8
6.2.5 Parity Protection ..........................................................................................................8
6.2.6 Atomic Accesses .........................................................................................................8
6.3 Data Cache and Mini-Data Cache Control ...................................................................................9
6.3.1 Data Memory State After Reset...................................................................................9
6.3.2 Enabling/Disabling .......................................................................................................9
6.3.3 Invalidate & Clean Operations .....................................................................................9
6.3.3.1 Global Clean and Invalidate Operation...................................................10
6.4 Re-configuring the Data Cache as Data RAM ............................................................................12
6.5 Write Buffer/Fill Buffer Operation and Control ............................................................................16
7 Configuration ........................................................................................... 1
7.1 Overview.......................................................................................................................................1
7.2 CP15 Registers.............................................................................................................................4
7.2.1 Register 0: ID and Cache Type Registers ...................................................................5
7.2.2 Register 1: Control and Auxiliary Control Registers ....................................................7
7.2.3 Register 2: Translation Table Base Register ...............................................................9
7.2.4 Register 3: Domain Access Control Register ..............................................................9
7.2.5 Register 4: Reserved ...................................................................................................9
7.2.6 Register 5: Fault Status Register...............................................................................10
7.2.7 Register 6: Fault Address Register............................................................................10
7.2.8 Register 7: Cache Functions .....................................................................................11
7.2.9 Register 8: TLB Operations .......................................................................................13
7.2.10 Register 9: Cache Lock Down ...................................................................................14
7.2.11 Register 10: TLB Lock Down .....................................................................................15
7.2.12 Register 11-12: Reserved..........................................................................................15
7.2.13 Register 13: Process ID.............................................................................................16
7.2.13.1 The PID Register Affect On Addresses ..................................................16
7.2.14 Register 14: Breakpoint Registers .............................................................................17
7.2.15 Register 15: Coprocessor Access Register ...............................................................18
7.3 CP14 Registers...........................................................................................................................20
7.3.1 Registers 0-3: Performance Monitoring .....................................................................20
7.3.2 Register 4-5: Reserved..............................................................................................20
7.3.3 Registers 6-7: Clock and Power Management ..........................................................21
7.3.4 Registers 8-15: Software Debug................................................................................22
8 System Management ............................................................................... 1
8.1 Clocking........................................................................................................................................1
8.2 Processor Reset ...........................................................................................................................3
8.2.1 Reset Sequence ..........................................................................................................3
8.2.2 Reset Effect on Outputs...............................................................................................4
8.3 Power Management......................................................................................................................5
8.3.1 Invocation ....................................................................................................................5
8.3.2 Signals Associated with Power Management..............................................................5
9 Interrupts .................................................................................................. 1
9.1 Introduction...................................................................................................................................1
9.2 External Interrupts ........................................................................................................................1