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6-2 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Data Cache
Figure 6-1. Data Cache Organization
way 0
way 1
way 31
32 bytes (cache line)
Set 31
CAM
DATA
way 0
way 1
way 31
32 bytes (cache line)
Set 1
CAM
DATA
way 0
way 1
way 31
32 bytes (cache line)
Set Index
Set 0
Tag
Data Address (Virtual)
31 109 54 210
Tag Set Index Word Byte
Word Select
CAM
DATA
Data Word
(4 bytes to Destination Register)
Byte Alignment
Sign Extension
Byte Select
This example shows
Set 0 being selected
by the set index.
CAM: Content Addressable Memory