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Developer’s Manual March, 2003 4-7
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Instruction Cache
4.3.3 Invalidating the Instruction Cache
The entire instruction cache along with the fetch buffers are invalidated by writing to
coprocessor 15, register 7. (See Table 7-12, “Cache Functions” on page 7-11 for the exact
command.) This command does not unlock any lines that were locked in the instruction cache nor
does it invalidate those locked lines. To invalidate the entire cache including locked lines, the
unlock instruction cache command needs to be executed before the invalidate command. This
unlock command can also be found in Table 7-14, “Cache Lockdown Functions” on page 7-14.
There is an inherent delay from the execution of the instruction cache invalidate command to
where the next instruction sees the result of the invalidate. The following routine can be used to
guarantee proper synchronization.
The Intel
®
80200 processor also supports invalidating an individual line from the instruction cache.
See Table 7-12, “Cache Functions” on page 7-11 for the exact command.
Example 4-3. Invalidating the Instruction Cache
MCR P15,0,R1,C7,C5,0 ; Invalidate the instruction cache and branch
; target buffer
CPWAIT
; The instruction cache is guaranteed to be invalidated at this point; the next
; instruction sees the result of the invalidate command.