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Developer’s Manual March, 2003 A-5
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Compatibility: Intel
®
80200 Processor vs. SA-110
A.3.6 Performance Differences
There exists significant performance differences in program execution between SA-110 and the
Intel
®
80200 processor. If an SA-110 application had operations that had specific timing
relationships, these relationships would not hold for the Intel
®
80200 processor. In all typical
applications, the Intel
®
80200 processor performance greatly exceeds that of SA-110.
The following is a list of all the new features introduced in the Intel
®
80200 processor that
significantly improve the instruction per cycle (IPC) number seen in SA-110. Any application
written for SA-110 will encounter these performance enhancing features.
• Data cache is non-blocking, which means execution does not stall for every data cache miss.
• Multiply instructions execute in parallel with other non-multiply instructions.
• The instruction and data cache size doubled.
• A branch target buffer was added to reduce branch latency.
Overall, the instruction timings specified in Section 14.4, “Instruction Latencies” on page 14-3 are
similar to the SA-110.
There are however, a few cases that may negatively impact the IPC number.
• Worst case branch latency increased from two to five cycles.
• The minimum result latency of loads that zero extend the result data increased from two to
three cycles.
• The minimum result latency of an ALU operation followed by a shift operation increased from
one to two cycles.
Keep in mind that the previous discussion was focusing on IPC differences. There is also the
frequency difference, which is targeted to give the Intel
®
80200 processor a 3X performance boost
over SA-110 alone.
A.3.7 System Control Coprocessor
Additional bits and registers were added to CP15 to support the added functionality of the Intel
®
80200 processor. Also, some system resources are controlled from CP14 registers. See Chapter 7,
“Configuration”, for more information.
A.3.8 New Instructions and Instruction Formats
Chapter 2, “Programming Model”, discusses new instructions and instruction formats. These
instructions would have generated Undefined faults on the SA-110.
A.3.9 Augmented Page Table Descriptors
Chapter 2, “Programming Model”, discusses how the Intel
®
80200 processor augments the SA-110
descriptors.