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A-2 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Compatibility: Intel
®
80200 Processor vs. SA-110
Feature / Parameter Brief Description or Note SA-110
Intel
®
80200
Processor
Main Execution Pipeline Scalar, in-order execution, single issue ••
• RISC Superpipeline
Pipeline with more than usual number of pipe
stages. Allows greater operating frequency.
(5 stage)
•
(7 stage)
• Out-of order completion Instructions may finish out of program order. •
• Concurrent execution in 3
pipes
Instructions may occupy the MAC, ALU, and
data-cache pipes concurrently.
•
• ALU
Number of cycles ALU takes to complete
instruction.
11
a
a. A 32-bit shift and ALU operation takes 1.5 cycles.
• Register Scoreboarding
Allows instructions in different pipelines to
execute as long as there are no data hazards.
•
• Dynamic branch prediction
128 entry branch table address cache holds
history of branches taken and not taken.
•
• Branch misprediction
penalty
(in cycles) 1 4
MAC Pipeline Handles all multiply operations •
• Dedicated 40-bit
accumulator
Allows 256 accumulates before scaling of data is
necessary.
•
• 1 cycle 16x32 MAC
sustained
•
• Early terminate
MAC may finish instruction and return results in
any of the MAC pipestages.
n/a •
Instruction Cache ••
• Geometry / Replacement
policy
Both the SA-110 and the Intel
®
80200 processor
are 32-way set associative with round-robin
replacement. They differ in size.
16K 32K
• Lockable by line
Instructions may be locked into the instruction
cache with line granularity, preventing future
eviction.
•
• Fetch buffers Buffer incoming external memory operations. •
Data Cache / Mini Data
Cache
• Replacement Policy round-robin round-robin
• Primary Data Cache
Geometry
Both SA-110 and
the Intel
®
80200 processor are
32-way set associative with round-robin
replacement. They differ in size.
16K,
32 ways
b
b. SA1100
32K,
32 way
• Mini Data Cache
Geometry
Set associative
512 bytes,
2 ways
2K,
2 ways
• Data RAM
Software can re-map portions of the data cache
into data-RAM on a line granularity.
•
• Hit under miss
Allow accesses to the data cache while there are
outstanding miss requests to external memory
•
• Write-back
Store operation that “hits” cache is not written to
external memory.
••
• Write-through
Store operations are written to external memory
even if cache is “hit”.
•
• Fill Buffer Buffer incoming external memory operations. ••
• Pending Buffer
Collects memory requests that “hit” an
outstanding load
•
• Write Buffer 8 entry write buffer ••
• Write Buffer coalescing
Number of entries that a new store request can
coalesce to in the write buffer
last entry All entries