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B-24 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Optimization Guide
B.4.3 Cache Considerations
B.4.3.1. Cache Conflicts, Pollution and Pressure
Cache pollution occurs when unused data is loaded in the cache and cache pressure occurs when
data that is not temporal to the current process is loaded into the cache. For an example, see
Section B.4.4.2., “Prefetch Loop Scheduling” below.
B.4.3.2. Memory Page Thrashing
Memory page thrashing occurs because of the nature of SDRAM. SDRAMs are typically divided
into 4 banks. Each bank can have one selected page where a page address size for current memory
components is often defined as 4k. Memory lookup time or latency time for a selected page address
is currently 2 to 3 bus clocks. Thrashing occurs when subsequent memory accesses within the same
memory bank access different pages. The memory page change adds 3 to 4 bus clock cycles to
memory latency. This added delay extends the prefetch distance correspondingly making it more
difficult to hide memory access latencies. This type of thrashing can be resolved by placing the
conflicting data structures into different memory banks or by paralleling the data structures such
that the data resides within the same memory page. It is also extremely important to insure that
instruction and data sections are in different memory banks, or they continually trash the memory
page selection.