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Developer’s Manual March, 2003 6-13
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Data Cache
Example 6-3. Locking Data into the Data Cache
; configured with C=1 and B=1
; R0 is the number of 32-byte lines to lock into the data cache. In this
; example 16 lines of data are locked into the cache.
; MMU and data cache are enabled prior to this code.
.macroCPWAIT
MRC P15, 0, R0, C2, C0, 0
MOV R0, R0
SUB PC, PC, #4
.endm
.macroDRAIN
MCR P15, 0, R0, C7, C10, 4 ; drain pending loads and stores
.endm
.macroLOCKLINE, Rx, Ry
; Write back the line if it's dirty in the cache
MCR P15, 0, \Rx, C7, C10, 1
; Flush/Invalidate the line from the cache
MCR P15, 0, \Rx, C7, C6, 1
; Load and lock 32 bytes of data located at [R1]
; into the data cache. Post-increment the address
; in R1 to the next cache line.
LDR \Ry, [\Rx], #32
.endm
; LockLines(int cache_lines, void *start_address)
.global LockLines
LockLines:
STMFDSP!, {R4-R6, LR}
MOV R6, R0
DRAIN
MOV R2, #0x1
MCR P15, 0, R2, C9, C2, 0 ; Put the data cache in lock mode
CPWAIT
LOOP1:
LOCKLINE R1, R2
SUBSR6, R6, #1; Decrement loop count
BEQ DONE
LOCKLINE R1, R3
SUBSR6, R6, #1; Decrement loop count
BEQ DONE
LOCKLINE R1, R4
SUBSR6, R6, #1; Decrement loop count
BEQ DONE
LOCKLINE R1, R5
SUBSR6, R6, #1; Decrement loop count
BNE LOOP1
; Turn off data cache locking
DONE:
DRAIN
MOV R2, #0x0
MCR P15, 0, R2, C9, C2, 0 ; Take the data cache out of lock mode.
CPWAIT
LDMFDSP!, {R4-R6, PC}