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13-36 March, 2003 Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Software Debug
13.14.3 LDIC Cache Functions
The Intel
®
80200 processor supports four cache functions that can be executed through JTAG.
Two functions allow an external host to download code into the main instruction cache or the mini
instruction cache through JTAG. Two additional functions are supported to allow lines to be
invalidated in the instruction cache. The following table shows the cache functions supported
through JTAG.
Invalidate IC line invalidates the line in the instruction cache containing specified virtual address.
If the line is not in the cache, the operation has no effect. It does not take any data arguments.
Invalidate Mini IC
1
invalidates the entire mini instruction cache. It does not effect the main
instruction cache. It does not require a virtual address or any data arguments.
Load Main IC and Load Mini IC write one line of data (8 ARM instructions) into the specified
instruction cache at the specified virtual address.
Each cache function is downloaded through JTAG in 33 bit packets. Figure 13-11 shows the packet
formats for each of the JTAG cache functions. Invalidate IC Line and Invalidate Mini IC each
require 1 packet. Load Main IC and Load Mini IC each require 9 packets.
Table 13-18. LDIC Cache Functions
Function Encoding
Arguments
Address # Data Words
Invalidate IC Line 0b000 VA of line to invalidate 0
Invalidate Mini IC 0b001 - 0
Load Main IC 0b010 VA of line to load 8
Load Mini IC 0b011 VA of line to load 8
RESERVED 0b100-0b111 - -
1. The LDIC Invalidate Mini IC function does not invalidate the BTB (like the CP15 Invalidate IC function) so software must do this manually
where appropriate.