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3.2 Reset Reason Resister (RSRR) and Watchdog Cycle Control Register (WTCR)
[bit 09, 08] WT1, 0
These bits specify the cycle of the watchdog timer. The bits and the cycles selected by the
bits have the relationships shown in Table 3.2.1. These bits are initialized when the entire
register is reset.
φ
is twice as large as X0 when GCR CHC is 1, and is the cycle of PLL oscillation frequency
when CHC is 0.
Table 3.2-1 Watchdog Timer Cycles Specified by WT1 and WT0
WT1 WT0 Minimum WPR write interval
required to suppress watchdog
resetting
Time from last 5AH write to WPR to
occurrence of watchdog resetting
00
φ ×
2
15
[Initial value]
φ ×
2
15
to
φ ×
2
16
01
φ ×
2
17
φ ×
2
17
to
φ ×
2
18
10
φ ×
2
19
φ ×
2
19
to
φ ×
2
20
11
φ ×
2
21
φ ×
2
21
to
φ ×
2
22