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15.3 DMAC Control Status Register (DACSR)
15.3 DMAC Control Status Register (DACSR)
The DMAC control status register (DACSR) is an internal register of the DMAC that
specifies control status information on the entire DMAC.
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Configuration of DMAC Control Status Register (DACSR)
The configuration of the DMAC control status register (DACSR) is shown below.
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Bit Functions of DMAC Control Status Register (DACSR)
[bit 31, 27, 23, 19, 15, 11, 7, 3] DERn (DMA ERror)
Each of these bits indicates that DMA transfer was interrupted because an error occurred in
the DMA request source for the corresponding channel n.
- 0: No error
- 1: An error occurred.
Error occurrence depnds on the DMA request source (resource). Errors do not occur in
some DMA request sources.
31 30 29 28 27 26 25 24
00000204H
R/W R/W R/W R/W R/W R/W R/W R/W
23 22 21 20 19 18 17 16
R/W R/W R/W R/W R/W R/W R/W R/W
15 14 13 12 11 10 9 8
R/W R/W R/W R/W R/W R/W R/W R/W
7654 3210
R/W R/W R/W R/W R/W R/W R/W R/W
DER7 DED7 DIE7 DOE7
DOE5DIE5DED5DER5
DOE3DIE3DER3 DED3
DOE1DIE1DER1 DED1
DED6
DED4
DED2
DED0
DIE6
DIE4
DIE2
DIE0
DER6
DER4
DER2
DER0
DOE6
DOE4
DOE2
DOE0
Initial value: 00000000H