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4.17 Bus Timing
❍
Bus width: 8 bits, access: half-words
Figure 4.17-6 Example 4 of Read Cycle Timing Chart
❍
Bus width: 8 bits, access: bytes
Figure 4.17-7 Example 5 of Read Cycle Timing Chart
BA1 BA2 BA1 BA2 BA1 BA2 BA1 BA2
CLK
A24
-
00 #0 #1 #2 #3
D31-24 #0 #1 #2 #3
D23-16
RDX
BA1 BA2 BA1 BA2 BA1 BA2 BA1 BA
CLK
A24-00 #0 #1 #2 #3
D31-24 #0 #1 #2 #3
D23-16
RDX