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CHAPTER 15 DMAC
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PDRR register
The suppression function for a DMA transfer operation specified via the HRCL register is valid
only when an interrupt request with higher priority is active. Therefore, if the interrupt request is
cleared by the interrupt handler program, suppression of the DMA transfer operation via the
HRCL register is canceled and the CPU may lose bus control.
The PDRR register in the clock control unit is used to clear an interrupt request, receive another
request, and suppress the DMA transfer operation.
When it is set to a value other than 0, DMA transfer is suppressed. For releasing the
suppression of DMA transfer, set the PDRR to 0.
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DMA Transfer Operation in Sleep Mode
When the CPU is in sleep state and a DMA transfer request is issued from an internal resource,
the DMAC performs a DMA transfer operation.
As the DMA transfer request signal from the internal resource serves as an interrupt request
signal, the CPU is released from sleep state. The sleep state is cleared even if the interrupt
level is set to interrupt inhibition level. When the DMA transfer operation ends, the CPU
resumes execution of the next instruction after that during which sleep state was entered.
When performing a transfer operation while the CPU is in sleep state, ensure through the
design of the program that the CPU checks the appropriate conditions and enters again sleep
state if required.
Control proceeds to the next processing step only when a specific address contains a specific
value.
If another cause was responsible, for example, if the CPU was released from sleep state
because of a DMA transfer operation after UART reception, sleep state is entered again.
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Transfer to DMC Internal Register
Do not specify a DMAC internal register as a transfer destination address.
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Continuous Transfer
In continuous transfer mode, write-back to the descriptor may occur even during a transfer,
depending on the internal bus buffer status of the device. In this case, the transfer operation
sleep_ mode:
ldi #50h, r0 ; Set SLEP bit.
ldi #481h, r1 ; STCR address
stb r0, @r0 ; Enter sleep mode.
;
; Determine the cause the CPU woke up.
; We assume here that an external interrupt has released the sleep
state.
ldi # address, r0
ldi # compared data, r1
ldub @r1, r0
and r0, r1
beq sleep_mode