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15.5 Descriptor Register in RAM ............................................................................................................... 332
15.6 DMAC Transfer Modes ...................................................................................................................... 335
15.7 Output of Transfer Request Acknowledgment and Transfer End signals .......................................... 338
15.8 Notes on DMAC ................................................................................................................................ 339
15.9 DMAC Timing Charts ......................................................................................................................... 342
15.9.1 Timing Charts of the Descriptor Access Block ............................................................................. 343
15.9.2 Timing Charts of Data Transfer Block .......................................................................................... 345
15.9.3 Transfer Stop Timing Charts in Continuous Transfer Mode ......................................................... 347
15.9.4 Transfer Termination Timing Charts ............................................................................................. 349
CHAPTER 16 FLASH MEMORY ...................................................................................... 351
16.1 Outline of Flash Memory .................................................................................................................... 352
16.2 Block Diagram of Flash Memory ........................................................................................................ 354
16.3 Flash Memory Status Register (FSTR) .............................................................................................. 355
16.4 Sector Configuration of Flash Memory .............................................................................................. 357
16.5 Flash Memory Access Modes ............................................................................................................ 359
16.6 Starting the Automatic Algorithm ....................................................................................................... 361
16.7 Execution Status of the Automatic Algorithm ..................................................................................... 364
APPENDIX .......................................................................................................................... 369
APPENDIX A I/O Maps ............................................................................................................................. 370
APPENDIX B Interrupt Vectors ................................................................................................................ 379
APPENDIX C Pin Status for Each CPU Status ......................................................................................... 383
APPENDIX D Notes on Using Little Endian Areas ................................................................................... 395
D.1 C Compiler (fcc911) ........................................................................................................................ 396
D.2 Assembler (fsm911) ........................................................................................................................ 399
D.3 Linker (flnk911) ............................................................................................................................... 401
D.4 Debuggers (sim911, eml911, and mon911) .................................................................................... 402
APPENDIX E Instructions ......................................................................................................................... 403
E.1 FR-Series Instructions ..................................................................................................................... 409
INDEX ................................................................................................................................. 425