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CHAPTER 2 CPU
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Restrictions on Branch Instructions with Delay Slots
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Instructions that can be placed in delay slots
An instruction that can be executed in the delay slot must satisfy all of the following conditions:
• One-cycle instruction
• Non-branch instruction
• Instruction whose operation is not affected even when the execution order changes
"One-cycle instruction" is an instruction for which 1, a, b, c, or d is indicated in the cycle count
column in the list of instructions.
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Step-trace-trap
No step-trace-trap is generated between the delay slot and the execution of the branch
instruction having the delay slot.
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Interrupt/NMI
No interrupt/NMI is accepted between the delay slot and the execution of the branch instruction
having the delay slot.
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Undefined-instruction exception
Even if an undefined instruction is placed in the delay slot, no undefined-instruction exception
occurs. The undefined instruction works as the NOP instruction