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2.7 Instruction Overview
2.7.2 Branch Instructions without Delay Slots
Instructions including branch instructions without delay slots are executed in order of
coding.
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Branch Instructions Without Delay Slots
The instructions represented as follows execute branching without delay slots:
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Theory of Operation of Branch Instructions Without Delay Slots
Instructions including branch instructions without delay slots are executed in order of coding.
The instruction provided immediately before the branch instruction is not executed before
branching.
[Example]
The number of execution cycles for a branch instruction without a delay slot is two cycles when
it involves branching, or one cycle when it does not involve branching.
Since no dummy instruction is placed in the delay slot, the instruction coding efficiency is better
than that of a branch instruction with a delay slot containing a NOP instruction.
Selecting an operation with a delay slot when an effective instruction can be placed in the delay
slot and selecting an operation without a delay slot otherwise can satisfy both execution speeds
and coding efficiency.
JMP @Ri CALL label12 CALL @Ri RET
BRA label9 BNO label9 BEQ label9 BNE label9
BC label9 BNC label9 BN label9 BP label9
BV label9 BNV label9 BLT label9 BGE label9
BLE label9 BGT label9 BLS label9 BHI label9
; Instruction list
ADD R1, R2 ;
BRA LABEL ; Branch instruction (without a delay slot)
MOV R2, R3 ; Not executed
:
LABEL : ST R3, @R4 ; Branch destination