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10.7 Asynchronous (Start-Stop) Mode
10.7 Asynchronous (Start-Stop) Mode
The UART handles data of only NRZ (nonreturn-to-zero) format.
Data transfer begins with a start bit (L-level data) for the specified number of data bits
in LSB first mode and ends with a stop bit (H-level data). When the external clock is
selected, always input the clock signal.
■
Format of Data Transferred in Asynchronous (Start-Stop) Mode
Figure 10.7-1 shows the format of data transferred in asynchronous (start-stop) mode.
The data length can be seven or eight bits in normal mode (mode 0), but must be eight bits in
multiprocessor mode (mode 1). An A/D bit is always added to data in multiprocessor mode
instead of a parity bit.
Figure 10.7-1 Format of Data Transferred in Asynchronous (Start-Stop) Mode (Mode 0 or 1)
❍
Receive operation
The UART performs a receive operation as long as the RXE bit (bit 1) of the SCR register is "1".
When a start bit appears on the receiving line, one data frame is received based on the data
format specified by the SCR register. If an error occurs after a frame has been received, an
error flag is set and the RDRF flag (bit 4 of the SSR register) is set subsequently, thereby
causing a receiver interrupt to the CPU if the RIE bit (bit 1) of the same SSR register has been
set to "1". Ensure in the program design that the flags of the SSR register are checked and the
SIDR register is read if normal reception is indicated, while the necessary processing for a
countermeasure is performed if an error is indicated.
The RDRF flag is cleared when the SIDR register is read.
❍
Transmit operation
Transmission data is written to the SODR register when the TDRE flag (bit 11) of the SSR
register is "1". When the TXE bit (bit 0) of the SCR register is "1", the written data is
transmitted.
When the data written to the SODR register is loaded to the transmission shift register and
transmission begins, the TDRE flag is set again so that the next instance of transmission data
can be written. If the TIE bit (bit 0) of the same SSR register has been set to "1", a transmitter
interrupt occurs in the CPU and a request to write transmission data to the SODR register is
issued.
The TDRE flag is cleared when data is written to the SODR register.
SI,SO
Start LSB MSB Stop
A/D Stop
Transferred data is 01001101
(Mode 0)
(Mode 1)
01
0
0
0
011 1
B