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1.1 MB91F109 Characteristics
• Automatic wait cycle: Any number of cycles (0 to 7) can be set for each area.
• Unused data and address terminals can be used as I/O ports.
• Support for little endian mode (selecting one of areas 1 to 5)
❍
DRAM interface
• 2-bank independent control (areas 4 and 5)
• Double CAS DRAM (normal DRAM interface), single CAS DRAM, and hyper DRAM
• Basic bus cycle: Five cycles in normal mode. Two-cycle access is enabled in high-speed
page mode.
• Programmable waveform: Automatic 1-cycle wait can be inserted into RAS or CAS.
• DRAM refresh
• CBR refresh (The interval can be set as desired using the 6-bit timer.)
• Self-refresh mode
• Support for 8-, 9-, 10-, or 12-line column address
• Choice between 2CAS/1WE and 2WE/1CAS
❍
DMAC (DMA controller)
• Eight channels
• Transfer cause: External terminal or internal resource interrupt request
• Transfer sequence
• Step transfer or block transfer
• Burst transfer or continuous transfer
• Transfer data length: Selectable from 8, 16, and 32 bits
• A temporary stop is enabled by an NMI/interrupt request.
❍
UART
• Independent three channels
• Full duplex double buffer
• Data length: 7 to 9 bits (no parity) or 6 to 8 bits (with parity)
• Choice between asynchronous (start-stop synchronization) communication and clock
asynchronous communication
• Multiprocessor mode
• Built-in 16-bit timer (U-Timer) as a baud rate generator, which can generate a desired baud
rates
• An external clock can be used as a transfer clock.
• Error detection: Parity error, frame error, and overrun
❍
A/D converter (successive approximation conversion type)
• 10-bit resolution, 4 channels
• Successive approximation conversion type: 5.6
µ
s
at 25 MHz
• Built-in sample and hold circuit
• Conversion mode: Selectable from single conversion, scan conversion, and repeat