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CHAPTER 4 BUS INTERFACE
4.1 Outline of Bus Interface
The bus interface controls the interface between external memory and I/O.
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Features of the Bus Interface
• 25-bit (32 megabytes) address output
• 6 independent banks to be set by chip select function
• Capable of setting a bank in an optional location in at least 64 kilobytes in the logical
address space
• Capable of setting six 32-megabyte areas with address and chip select pins
• Capable of setting a 16-bit or 8-bit bus width for each chip select area
• Inserting programmable, automatic memory wait (7 or less cycles)
• Support of DRAM interface
• 3 types of DRAM interface
Double CAS DRAM (usual DRAM interface)
Single CAS DRAM
Hyper DRAM
• Independent control of 2 banks (RAS and CAS control signals)
• Capable of selecting 2CAS/1WE and 1CAS/2WE DRAMs
• Support of high-speed page mode
• Support of CBR or selfrefresh
• Programmable waveforms
• Capable of using unused address or data pins as I/O ports
• Support of little endian mode