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CHAPTER 2 CPU
2.8.1 EIT Interrupt Levels
The EIT interrupt levels range from 0 to 31, which are managed using five bits.
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Interrupt Levels
Table 2.8.1 summarizes the assignments of the EIT interrupt levels.
Operation can be performed on levels 16 to 31.
Undefined-instruction exceptions, coprocessor nonexistent traps, coprocessor error traps, and
INT instructions are not affected by interrupt levels. ILM is not changed either.
Table 2.8-1 Interrupt Level
Level Cause Remarks
Binary Decimal
00000 0 (Reserved by the system)
When the original value of ILM is
one from 16 to 31, no value within
this range can be set in ILM by a
program.
: : :
: : :
00011 3 (Reserved by the system)
00100 4
INTE instruction
Step-trace-trap
00101 5 (Reserved by the system)
: : :
: : :
01110 14 (Reserved by the system)
01111 15 NMI (for the user)
10000 16 Interrupt When ILM is set, user interrupts are
inhibited.
10001 17 Interrupt
: : :
: : :
11110 30 Interrupt
11111 31 - When ICR is set, interrupts are
inhibited.