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4.11 Refresh Control Register (RFCR)
[bit 2] STR (STaRt bit)
The STR bit controls or starts and stops the downward counter.
0: STOP (initial value)
1: START
When the STR is set, the REL value is loaded into the downward counter.
When the REFE bit of the DMCR and the STR bit are set to "1", the CRB refresh operation is
performed.
[bit 1 and 0] CKS (ClocK Select bit)
The CKS bits select a clock source for the downward counter.
The downward counter uses the divide-by-32 output
Φ
of the timebase timer as a clock.
CKS1 CKS0 Source clock Maximum number of clocks
00
Φ
(initial value
value)
2
6
(REL5 - 0: 6 bits) x 32 (divide-by-32 output) = 2048
01
Φ
/8 2
6
(REL5 - 0: 6 bits) x 32 (divide-by-32 output) x 8 = 16384
1 0 reserved
1 1 reserved