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2.8 EIT (Exception, Interrupt, and Trap)
■
I Flag
The I flag specifies whether to enable or disable interrupts. It is provided at bit 4 of PS register
CCR.
■
Interrupt Level Mask Register (ILM)
ILM is a part of the PS register (bits 16 to 20) that holds an interrupt level mask value.
Of the interrupt requests input to the CPU, only those with higher interrupt levels than the level
indicated by the ILM are accepted.
The level values range in descending order from 0 (00000
B
) to 31 (11111
B
).
The values that can be set from a program are limited. When the original value is in the range
from 16 to 31, a new value that can be set must be in the same range, i.e., from 16 to 31. If an
instruction that sets a value from 0 to 15 is executed, the "specified value + 16" is returned.
When the original value is in the range from 0 to 15, a desired value from 0 to 31 can be set.
<Note>
Use the SETILM instruction to set the level to the ILM register.
■
Level Mask for Interrupt/NMI
When an NMI or interrupt request is issued, the interrupt level (see Table 2.8.1) of the interrupt
cause is compared with the level mask value indicated by the ILM. The interrupt request is
masked and not accepted if the following condition is satisfied:
• Interrupt level held by the cause is greater than or equal to Level mask value
Value Function
0 Disables interrupts.
The bit is cleared to 0 when the INT instruction is executed.
(The value before the bit is cleared is saved to the stack.)
1 Enables interrupts.
The masking of interrupt requests is controlled by the value held in the ILM.