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APPENDIX E Instructions
■
Other Instructions
Table E.1-13 Other Instructions
Mnemonic Type OP CYCLE NZVC Operation Remarks
NOP E 9F-A 1 ---- Remains unchanged.
ANDCCR#u8
ORCCR #u8
D
D
83
93
c
c
CCCC
CCCC
CCR and u8 --> CCR
CCR or u8 --> CCR
STILM #u8 D 87 1 ---- i8 --> ILM
ILM immediate value setting
ADDSP #s10*1 D A3 1 ---- R15 += s10
ADD SP instruction
EXTSB Ri
EXTUB Ri
EXTSH Ri
EXTUH Ri
E
E
E
E
97-8
97-9
97-A
97-B
1
1
1
1
----
----
----
----
Code expansion 8 --> 32
bits
Zero expansion 8 --> 32
bits
Code expansion 16 --> 32
bits
Zero expansion 16 --> 32
bits
LDM0 (reglist)
LDM1 (reglist)
*LDM (reglist)*2
D
D
8C
8D
----
----
----
(R15) -->reglist,
R15 increment
(R15) -->reglist,
R15 increment
(R15) -->reglist,
R15 increment
Multiple load R0-R7
Multiple load R8-R15
Multiple load R0-R15
STM0 (reglist)
STM1 (reglist)
*STM (reglist)*3
D
D
8E
8F
----
----
----
R15 decrement,
reglist-->(R15)
R15 decrement,
Reglist-->(R15)
R15 decrement,
reglist-->(R15)
Multiple store R0-R7
Multiple store R8-R15
Multiple store R0-R15
ENTER #u10*4 D 0F 1+a ---- R14 --> (R15 - 4),
R15 - 4 --> R14,
R15 - u10 --> R15
Entrance processing of function
LEAVE E 9F-9 b ---- R14 + 4 --> R15,
(R15 - 4) --> R14
Exit processing of function
XCHB @Rj, Ri A 8A 2a ---- Ri --> TEMP
(Rj) --> Ri
TEMP --> (Rj)
For semaphore management
*1: The assembler converts s10 to s8 by calculating s10/4, then sets the value in s8. S10 is signed.
*2: If a register from R0 to R7 is specified in reglist, LDM0 is created. If a register from R8 to R15 is
specified in reglist, LDM1 is created. Both LDM0 and LDM1 may be created.
*3: If a register from R0 to R7 is specified in reglist, STM0 is created. If a register from R8 to R15 is
specified in reglist, STM1 is created. Both STM0 and STM1 may be created.
*4: The assembler converts u10 to u8 by calculating u10/4, then sets a value in u8. U10 is signed.