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CHAPTER 4 BUS INTERFACE
In an 8-bit data bus width, write data is output from D31 to D24.
• RAS is similar to that at read cycles.
• CAS is also similar to that at read cycles.
•WE
is a write strobe signal to the DRAM. For the 1CAS/2WE, WEL represents WE of the
upper address side ("0" of lower 1 bit), and WEH
represents WE of the lower address side
("1" of lower 1 bit).
This signal is output in write cycles, asserted at the rising edge of Q4, and negated at the
rising edge of the cycle next to Q5.
• In write cycles, RDX stays at "H".
• CS4X and CS5X are output from the rising edge of the Q1 cycle.
• DACK0 to DACK2 and E0P0 to E0P2 are output in external bus cycles. Whether to output
these signals is determined by settings in the DMAC register. The output time is the same
as CAS.