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4.17 Bus Timing
• Output of CS0X to CS5X (area chip select) signals is asserted from the beginning (BA1) of
bus cycles; that is, at the same time as A24-A00. The CS0X to CS5X signals are generated
from decoded output addresses and remain unchanged unless those addresses change,
thereby changing the chip select areas set by the ASR and AMR. Note that one of these
signals is always asserted.
• DACK0 to DACK2 and E0P0 to E0P2 are output in the DMA external bus cycles. The
DMAC register specifies whether to output these signals. The output time is the same as for
RDX.