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CHAPTER 15 DMAC
These bits are initialized to "0" by resetting.
These bits can be both read and written, but can only be set to "0".
A Read Modify Write instruction always reads "1" from each of these bits.
[bit 30, 26, 22, 18, 14, 10, 6, 2] DEDn (DMA EnD)
Each of these bits indicates whether DMA transfer in the corresponding channel (n) is
finished.
- 0: DMA transfer has not been finished.
- 1: The counter reached 0 or an error occurred in the transfer request source.
These bits are initialized to "0" by resetting.
These bits can be both read and written, but can only be set to "0".
A Read Modify Write instruction always reads "1" from each of these bits.
[bit 29, 25, 21, 17, 13, 9, 5, 1] DIEn (DMA Operation Enable)
Each of these bits specifies whether to cause an interrupt request when DMA transfer is
finished in the corresponding channel n (when DEDn is 1).
- 0: Do not cause an interrupt request.
- 1: Cause an interrupt request.
These bits are initialized to "0" by resetting.
These bits can be both read and written.
[bit 28, 24, 20, 16, 12, 8, 4, 0] DOEn (DMA Operation Enable)
Each of these bits specifies whether to enable DMA transfer in the corresponding channel n.
- 0: Disable DMA transfer.
- 1: Enable DMA transfer.
DOEn is cleared when DMA transfer in the corresponding channel is completed.
If there are simultaneous attempts to clear DOEn because of the completion of transfer
respectively a bus write operation, setting has priority.
These bits are initialized to "0" by resetting.
These bits can be both read and written.