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11.4 A/D Converter Operation
In continuous conversion mode, the A/D converter continues conversion until the BUSY bit is
set to "0". Writing "0" to the BUSY bit forcibly terminates A/D conversion.
Note that forced termination interrupts conversion in progress.
When conversion is forcibly terminated, the data register contains previously converted data.
❍
Convert-and-stop mode
In convert-and-stop mode, the A/D converter sequentially converts the analog inputs specified
by the ANS and ANE bits of the ADCS register and stops whenever conversion of the analog
input from one channel is completed. The converter restarts conversion at the next start cause.
When conversion is completed up to the end channel specified by the ANE bits, the converter
returns to the ANS analog input and continues A/D conversion.
If the start and end channels are the same (ANS = ANE), conversion of the analog input from
only one channel is repeated.
Example:
ANS = 000, ANE = 011
Start --> AN0 --> stop --> start --> AN1 --> stop --> start --> AN2 --> stop --> start --> AN3 -->
stop --> start --> AN0 ... --> iteration
ANS = 010, ANE = 010
Start --> AN2 --> stop --> start --> AN2 --> stop --> start --> AN2 ... --> iteration
Only the start causes set by the STS1 and STS0 bits are applicable to the above operation.
Convert-and-stop mode can be used to synchronize the beginning of conversion.