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Table 8.3-1 Correspondences between the Interrupt Level Setting Bits and Interrupt Levels ................... 229
Table 8.5-1 Relationships among Interrupt Causes, Numbers, and Levels (1/2) ...................................... 231
Table 8.5-2 Relationships among Interrupt Causes, Numbers, and Levels (2/2) ...................................... 232
Table 8.7-1 Settings for the Interrupt Levels for which a Hold Request Cancel Request is Issued ........... 235
Table 10.2-1 Selection of UART Operation Modes ...................................................................................... 248
Table 10.6-1 UART Operation Modes ......................................................................................................... 255
Table 10.11-1 Baud Rates and U-TIMER Reload Values in Asynchronous (Start-Stop) Mode .................... 265
Table 10.11-2 Baud Rates and U-TIMER Reload Values in CLK Synchronous Mode .................................. 265
Table 11.2-1 Selecting the Causes for Starting the A/D Converter ............................................................. 271
Table 11.2-2 Selecting the A/D Converter Operation Mode ........................................................................ 272
Table 11.2-3 Setting the A/D Conversion Start Channel ............................................................................. 273
Table 11.2-4 Setting the A/D Conversion End Channel ............................................................................... 273
Table 12.2-1 CSL Bit Setting Clock Source ................................................................................................. 284
Table 13.3-1 Bit Positions and Returned Values (Decimal) ......................................................................... 296
Table 14.3-1 Selection of the Count Clock .................................................................................................. 305
Table 14.3-2 PWM Output When "1" is Written to PGMS ............................................................................ 305
Table 14.3-3 Selection of Trigger Input Edge .............................................................................................. 305
Table 14.3-4 Selection of Interrupt Causes ................................................................................................. 306
Table 14.3-5 Specification of the Polarity of the PWM Output and the Edge .............................................. 306
Table 14.7-1 Selection of Ch3 Trigger Input ................................................................................................ 312
Table 14.7-2 Selection of Ch2 Trigger Input ................................................................................................ 312
Table 14.7-3 Selection of Ch1 Trigger Input ................................................................................................ 313
Table 14.7-4 Selection of Ch0 Trigger Input ................................................................................................ 313
Table 15.2-1 Channel Descriptor Addresses ............................................................................................... 326
Table 15.4-1 Selection of Transfer Input Detection Levels .......................................................................... 330
Table 15.4-2 Specification of Transfer Request Acknowledgment Output .................................................. 330
Table 15.4-3 Specification of Transfer End Output ...................................................................................... 331
Table 15.5-1 Specification of Transfer Source or Destination Address Update Modes ............................... 333
Table 15.5-2 Address Increment/Decrement Unit ........................................................................................ 333
Table 15.5-3 Specification of Transfer Data Size ........................................................................................ 333
Table 15.5-4 Transfer Mode Specification ................................................................................................... 334
Table 15.9-1 Codes Used in the Timing Charts ........................................................................................... 342
Table 16.4-1 Sector Addresses ................................................................................................................... 358
Table 16.6-1 Commands ............................................................................................................................. 361
Table 16.7-1 Statuses of the Hardware Sequence Flag .............................................................................. 365
Table A-1 I/O Map (1/6) ........................................................................................................................... 371
Table A-2 I/O Map (2/6) ........................................................................................................................... 372
Table A-3 I/O Map (3/6) ........................................................................................................................... 373