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FIGURES
Figure 1.2-1 General Block Diagram of MB91F109 ........................................................................................ 6
Figure 1.3-1 Outside Dimensions of FPT-100P-M06 ...................................................................................... 7
Figure 1.3-2 Outside Dimensions of FPT-100P-M05 ...................................................................................... 8
Figure 1.3-3 Outside Dimensions of BGA-112P-M01 ..................................................................................... 9
Figure 1.4-1 QFP-100 Pin Arrangements ..................................................................................................... 10
Figure 1.4-2 LQFP-100 Pin Arrangements ................................................................................................... 11
Figure 1.4-3 FBGA-112 Pin Arrangements ................................................................................................... 12
Figure 1.7-1 MB91F109 Memory Map ......................................................................................................... 24
Figure 1.8-1 Example of Using an External Clock (Normal Method) ............................................................ 26
Figure 1.8-2 Example of Using an External Clock (Possible at 12.5 MHz or Lower) .................................... 27
Figure 2.2-1 Internal Architecture .................................................................................................................. 31
Figure 2.2-2 Instruction Pipeline ................................................................................................................... 32
Figure 2.3-1 Configuration of general-purpose registers .............................................................................. 33
Figure 2.3-2 Configuration of special registers ............................................................................................. 34
Figure 2.3-3 Configuration of General-Purpose Registers ............................................................................ 35
Figure 2.3-4 Configuration of Special Registers ........................................................................................... 36
Figure 2.4-1 Data Mapping in Bit Ordering Mode ......................................................................................... 42
Figure 2.4-2 Data Mapping in Byte Ordering Mode ...................................................................................... 42
Figure 2.6-1 MB91F109 Memory Map .......................................................................................................... 44
Figure 2.6-2 Memory Map Common to the FR Series. ................................................................................. 45
Figure 2.8-1 Example of Interrupt Stack ....................................................................................................... 58
Figure 2.8-2 Example of Multiple EIT Processing ......................................................................................... 63
Figure 2.10-1 Mode Register Configuration .................................................................................................... 70
Figure 3.1-1 Clock Generator and Controller Registers ................................................................................ 74
Figure 3.1-2 Block Diagram of the Clock Generator and Controller .............................................................. 75
Figure 3.9-1 Gear Controller Block Diagram ................................................................................................. 87
Figure 3.9-2 Clock Selection Timing Chart ................................................................................................... 89
Figure 3.10-1 Stop Controller Block Diagram ................................................................................................. 92
Figure 3.10-2 Sleep Controller Block Diagram ................................................................................................ 95
Figure 3.10-3 Standby Mode State Transition ................................................................................................ 98
Figure 3.11-1 Watchdog Timer Block Diagram ............................................................................................... 99
Figure 3.11-2 Watchdog Timer Operating Timing ......................................................................................... 100
Figure 3.11-3 Timebase Timer Counter ........................................................................................................ 100
Figure 3.12-1 Block Diagram of Reset Source Hold Circuit .......................................................................... 101
Figure 3.13-1 DMA Suppression Circuit Block Diagram ............................................................................... 103