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APPENDIX C Pin Status for Each CPU Status
Table C-5 Pin Status in Single Chip Mode
Pin name Function During sleep During stop — Reset time
HIZX=0
HIZX=1
P20 to P27 Port Previous status
retained
Previous status
retained
Output Hi-Z/
Input fixed to 0
Output Hi-Z/
Input
allowed for
all pins
P30 to P37
P40 to P47
P50 to P57
P60 to P67
P70 EOP0 P: Previous
status retained
F: EOP output
P80 Port Previous status
retained
P81
P82
P83
P84
P85
PA0
PA1 to
PA2
PA3 EOP1 P: Previous
status retained
F: EOP output
PA4 to
PA5
Port Previous status
retained
PA6
PB0
PB1
PB2
PB3
PB4 EOP2 P: Previous
status retained
F: EOP output