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CHAPTER 2 CPU
[bit 3] N: Negative flag
This bit indicates a sign applicable when the operation result is assumed to be an integer
that is represented in two’s complement.
0: Indicates that the operation result is a positive value.
1: Indicates that the operation result is a negative value.
The initial value after resetting is undefined.
[bit 2] Z: Zero flag
This bit indicates whether the operation result is 0.
0: Indicates that the operation result is a value other than 0.
1: Indicates that the operation result is 0.
The initial value after resetting is undefined.
[bit 1] V: Overflow flag
This bit assumes that the operands used for operation are each an integer represented in
two’s complement and indicates whether an overflow occurred as the result of operation.
0: Indicates that no overflow occurred as the result of operation.
1: Indicates that an overflow occurred as the result of operation.
The initial value after resetting is undefined.
[bit 0] C: Carry flag
This bit indicates whether carry from the most significant bit or borrow occurred during
operation.
0: Indicates that no carry and borrow occurred.
1: Indicates that carry or borrow occurred.
The initial value after resetting is undefined.
❍
System condition code register (SCR)
The configuration of the system condition code register (SCR) is as follows:
[bit 10, 9] D1, D0: Step division flag
These bits hold intermediate data during execution of step division.
They must not be changed during execution of step division.
When other processing is performed during execution of step division, continued operation
for step division is guaranteed by saving and restoring the value in the PS register.
The initial value after resetting is undefined.
When the DIV0S instruction is executed, the dividend and divisor are referenced and set.
Execution of the DIV0U instruction forcibly clears the bits.
10
D1 D0 XX0
B
[Initial value]
T
98